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AT80SND2CMP3B Datasheet(PDF) 232 Page - ATMEL Corporation |
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AT80SND2CMP3B Datasheet(HTML) 232 Page - ATMEL Corporation |
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232 / 242 page  232 4341H–MP3–10/07 AT8xC51SND2C/MP3B 24.4.4.3 Waveforms Figure 24-26. FLASH Memory - ISP Waveforms Note: 1. ISP must be driven through a pull-down resistor (see Section “In System Programming”, page 218). Figure 24-27. FLASH Memory - Internal Busy Waveforms 24.4.5 External Clock Drive and Logic Level References 24.4.5.1 Definition of symbols Table 24-26. External Clock Timing Symbol Definitions 24.4.5.2 Timings Table 24-27. External Clock AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C RST T SVRL ISP(1) T RLSX FBUSY bit T BHBL Signals Conditions C Clock H High L Low X No Longer Valid Symbol Parameter Min Max Unit TCLCL Clock Period 50 ns TCHCX High Time 10 ns TCLCX Low Time 10 ns TCLCH Rise Time 3 ns TCHCL Fall Time 3 ns TCR Cyclic Ratio in X2 mode 40 60 % |
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