PIC17C752-08SLASHCL datasheet(294/328 Pages) MICROCHIP

294 / 328 page

PIC17C7XX

DS30289A-page 294

FIGURE F-4:

CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)

U - 0

R - 1

R/W - 1

R - 1

R/W - 0

R/W - 1

—

STKAV GLINTD

POR

BOR

R = Readable bit

W = Writable bit

U = Unimplemented bit,

Read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7-6:

Unimplemented: Read as '0'

bit 5:

STKAV: Stack Available bit

This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh

→ 0h (stack overﬂow).

1 = Stack is available

0 = Stack is full, or a stack overﬂow may have occurred

(Once this bit has been cleared by a stack overﬂow, only a device reset will set this bit)

bit 4:

GLINTD: Global Interrupt Disable bit

This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can

cause an interrupt.

1 = Disable all interrupts

0 = Enables all un-masked interrupts

bit 3:

TO: WDT Time-out Status bit

1 = After power-up or by a CLRWDT instruction

0 = A Watchdog Timer time-out occurred

bit 2:

PD: Power-down Status bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 1:

POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set by software after a Power-on Reset occurs)

bit 0:

BOR: Brown-out Reset Status bit

When BODEN conﬁguration bit is set (enabled):

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set by software)

When BODEN conﬁguration bit is clear (disabled):

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