PIC17C752-08SLASHCL datasheet(184/328 Pages) MICROCHIP

184 / 328 page

PIC17C7XX

DS30289A-page 184

16.3

Configuring Analog Port Pins

The ADCON1, and DDR registers control the operation

of the A/D port pins. The port pins that are desired as

analog inputs must have their corresponding DDR bits

set (input). If the DDR bit is cleared (output), the digital

output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS2:CHS0 bits and the DDR bits.

Note 1: When reading the port register, any pin

conﬁgured as an analog input channel will

read as cleared (a low level). Pins conﬁg-

ured as digital inputs, will convert an ana-

log input. Analog levels on a digitally

conﬁgured input will not affect the conver-

sion accuracy.

Note 2: Analog levels on any pin that is deﬁned as

a digital input (including the AN15:AN0

pins), may cause the input buffer to con-

sume current that is out of the devices

speciﬁcation.

16.4

A/D Conversions

Example 16-2 shows how to perform an A/D conver-

sion. The PORTF and lower four PORTG pins are con-

ﬁgured as analog inputs. The analog references

(VREF+ and VREF-) are the device AVDD and AVSS. The

A/D interrupt is enabled, and the A/D conversion clock

is FRC. The conversion is performed on the RG3/AN0

pin (channel 0).

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The A/D result register

pair will NOT be updated with the partially completed

A/D conversion sample. That is, the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers). After the A/D conversion

is aborted, a 2TAD wait is required before the next

acquisition is started. After this 2TAD wait, acquisition

on the selected channel is automatically started.

In Figure 16-6, after the GO bit is set, the ﬁrst time seg-

mant has a minimum of TCY and a maximum of TAD.

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

EXAMPLE 16-2: A/D CONVERSION

FIGURE 16-6: A/D CONVERSION TAD CYCLES

MOVLB

; Bank 5

CLRF

ADCON1, F

; Configure A/D inputs, All analog, TAD = Fosc/8, left just.

MOVLW

0x01

; A/D is on, Channel 0 is selected

MOVWF

ADCON0

;

MOVLB

; Bank 4

BCF

PIR2, ADIF

; Clear A/D interrupt flag bit

BSF

PIE2, ADIE

; Enable A/D interrupts

BSF

INTSTA, PEIE

; Enable peripheral interrupts

BCF

CPUSTA, GLINTD

; Enable all interrupts

;

Ensure that the required sampling time for the selected input channel has elapsed.

;

Then the conversion may be started.

;

MOVLB

; Bank 5

BSF

ADCON0, GO

; Start A/D Conversion

;

The ADIF bit will be set and the GO/DONE bit

;

is cleared upon completion of the A/D Conversion

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9

Set GO bit

Holding capacitor is disconnected from analog input (typically 100 ns)

holding capacitor is connected to analog input.

TAD10 TAD11

Tcy to TAD

GO bit is cleared,

Next Q4: ADRES is loaded,

ADIF bit is set,

Conversion Starts

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