PIC17C752-08SLASHCL datasheet(219/328 Pages) MICROCHIP

219 / 328 page

DS30289A-page 219

PIC17C7XX

RETFIE

Return from Interrupt

Syntax:

[

label ]

RETFIE

Operands:

None

Operation:

TOS

→ (PC);

→ GLINTD;

PCLATH is unchanged.

Status Affected:

GLINTD

Encoding:

0000

0101

Description:

Return from Interrupt. Stack is POP’ed

and Top of Stack (TOS) is loaded in the

PC. Interrupts are enabled by clearing

the GLINTD bit. GLINTD is the global

interrupt disable bit (CPUSTA<4>).

Words:

Cycles:

Q Cycle Activity:

Decode

operation

Clear

GLINTD

POP PC

from stack

operation

Example:

RETFIE

After Interrupt

TOS

GLINTD =

RETLW

Return Literal to WREG

Syntax:

[

label ]

RETLW k

Operands:

≤ k ≤ 255

Operation:

→ (WREG); TOS → (PC);

PCLATH is unchanged

Status Affected:

None

Encoding:

1011

0110

kkkk

Description:

WREG is loaded with the eight bit literal

'k'. The program counter is loaded from

the top of the stack (the return address).

The high address latch (PCLATH)

remains unchanged.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal 'k'

Process

Data

POP PC

from stack,

Write to

WREG

operation

Example:

CALL TABLE ; WREG contains table

;

offset value

;

WREG now has

;

table value

TABLE

ADDWF PC

; WREG = offset

RETLW k0

; Begin table

RETLW k1

;

RETLW kn

; End of table

Before Instruction

WREG

0x07

After Instruction

WREG

value of k7

PIC17C752-08/CL Datasheet(PDF) 219 Page - Microchip Technology

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