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PIC18C658T-E/CL Datasheet(PDF) 129 Page - Microchip Technology

Part # PIC18C658T-E/CL
Description  High-Performance Microcontrollers with CAN Module
PDF  366 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18C658T-E/CL Datasheet(HTML) 129 Page - Microchip Technology

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 2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 129
PIC18CXX8
14.3.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE registers) clear to avoid false interrupts
and should clear the flag bit CCP1IF, following any
such change in operating mode.
14.3.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 14-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
14.3.5
CAN MESSAGE RECEIVED
The CAN capture event occurs when a message is
received in either receive buffer. The CAN module pro-
vides a rising edge to the CCP module to cause a cap-
ture event. This feature is provided to time-stamp the
received CAN messages.
EXAMPLE 14-1: CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
CLRF
CCP1CON, F
; Turn CCP module off
MOVLW
NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF
CCP1CON
; Load CCP1CON with
; this value
CCPR1H
CCPR1L
TMR1H
TMR1L
Set Flag bit CCP1IF
TMR3
Enable
Q’s
CCP1M3:CCP1M0
CCP1 Pin
Prescaler
÷ 1, 4, 16
and
edge detect
TMR3H
TMR3L
TMR1
Enable
T3CCP2
T3CCP2
CCPR2H
CCPR2L
TMR1H
TMR1L
Set Flag bit CCP2IF
TMR3
Enable
Q’s
CCP2M3:CCP2M0
CCP2 Pin
Prescaler
÷ 1, 4, 16
and
edge detect
TMR3H
TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
RXB0IF or
RXB1IF
CCP1CON<3:0>
Note:
I/O pins have diode protection to VDD and VSS.



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