PIC17C44-08SLASHP datasheet(120/240 Pages) MICROCHIP

120 / 240 page

PIC17C4X

DS30412C-page 120

CPFSLT

Compare f with WREG,

skip if f < WREG

Syntax:

[

label ] CPFSLT

Operands:

≤ f ≤ 255

Operation:

(f) –

(WREG),

skip if (f) < (WREG)

(unsigned comparison)

Status Affected:

None

Encoding:

0011

0000

ffff

Description:

Compares the contents of data memory

location 'f' to the contents of WREG by

performing an unsigned subtraction.

If the contents of 'f' < the contents of

WREG, then the fetched instruction is

discarded and an NOP is executed

instead making this a two-cycle instruc-

tion.

Words:

Cycles:

1 (2)

Q Cycle Activity:

Decode

Read

Execute

NOP

If skip:

Forced NOP

NOP

Execute

NOP

Example:

HERE

CPFSLT REG

NLESS

LESS

Before Instruction

Address (HERE)

After Instruction

If REG

WREG;

Address (LESS)

If REG

≥

WREG;

Address (NLESS)

DAW

Decimal Adjust WREG Register

Syntax:

[

label] DAW

f,s

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

If [WREG<3:0> >9] .OR. [DC = 1] then

WREG<3:0> + 6

→ f<3:0>, s<3:0>;

else

WREG<3:0>

→ f<3:0>, s<3:0>;

If [WREG<7:4> >9] .OR. [C = 1] then

WREG<7:4> + 6

→ f<7:4>, s<7:4>

else

WREG<7:4>

→ f<7:4>, s<7:4>

Status Affected:

Encoding:

0010

111s

ffff

Description:

DAW adjusts the eight bit value in

WREG resulting from the earlier addi-

tion of two variables (each in packed

BCD format) and produces a correct

packed BCD result.

s = 0:

Result is placed in Data

memory location 'f' and

WREG.

s = 1:

Result is placed in Data

memory location 'f'.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Execute

Write

and other

speciﬁed

Example1:

DAW

REG1, 0

Before Instruction

WREG

0xA5

REG1

After Instruction

WREG

0x05

REG1

0x05

Example 2:

Before Instruction

WREG

0xCE

REG1

After Instruction

WREG

0x24

REG1

0x24

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