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EM341-RTR Datasheet(PDF) 110 Page - Silicon Laboratories |
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EM341-RTR Datasheet(HTML) 110 Page - Silicon Laboratories |
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110 / 237 page  EM341 Rev 1.0 111 SC1_RXERRA: DMA First Receive Error Register A SC2_RXERRA: DMA First Receive Error Register A Register 8.31. SCx_RXERRA SC1_RXERRA: DMA First Receive Error Register A SC2_RXERRA: DMA First Receive Error Register A Bit 31 30 29 28 27 26 25 24 Name 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 0 SC_RXERRA Bit 7 6 5 4 3 2 1 0 Name SC_RXERRA Bitname Bitfield Access Description SC_RXERRA [13:0] R The offset from the start of DMA receive buffer A of the first byte received with a parity, frame, or overflow error. Note that an overflow error occurs at the input to the receive FIFO, so this offset is 4 bytes before the overflow position. If there is no error, it reads zero. This register will not be updated by subsequent errors until the buffer unloads and is reloaded, or the receive DMA is reset. |
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