STM32F303VE datasheet(135/184 Pages) STMICROELECTRONICS

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STM32F303xD STM32F303xE

Electrical characteristics

161

SPI/I2S characteristics

Unless otherwise specified, the parameters given in Table 73 for SPI or in Table 74 for I2S

are derived from tests performed under ambient temperature, fPCLKx frequency and VDD

supply voltage conditions summarized in Table 19.

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).

Table 73. SPI characteristics(1)

Symbol

Parameter

Conditions

Min

Typ.

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode 2.7 V<VDD<3.6 V,

SPI1/4

MHz

Master mode 2 V<VDD<3.6 V,

SPI1/2/3/4

Slave mode 2 V<VDD<3.6 V,

SPI1/4

Slave mode 2 V<VDD<3.6 V,

SPI1/2/3/4

Slave mode transmitter/full duplex

2 V<VDD<3.6 V, SPI1/2/3/4

16.5(2)

Slave mode transmitter/full duplex

2.7 V<VDD<3.6 V, SPI1/4

22.5(2))

Duty(SCK)

Duty cycle of SPI clock

frequency

Slave mode

tsu(NSS)

NSS setup time

Slave mode, SPI presc = 2

4*Tpclk

th(NSS)

NSS hold time

Slave mode, SPI presc = 2

2*Tpclk

tw(SCKH)

tw(SCKL)

SCK high and low time

Master mode

Tpclk-2

Tpclk

Tpclk+2

tsu(MI)

Data input setup time

Master mode

tsu(SI)

Slave mode

th(MI)

Data input hold time

Master mode

6.5

th(SI)

Slave mode

4.5

ta(SO)

Data output access time

Slave mode

tdis(SO)

Data output disable time

Slave mode

tv(SO)

Data output valid time

Slave mode 2.7 V<VDD<3.6 V

Slave mode 2 V<VDD<3.6 V

tv(MO)

Master mode

4.5

th(SO)

Data output hold time

Slave mode

th(MO)

Master mode

1. Data based on characterization results, not tested in production.

2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into

SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a

master having tsu(MI) = 0 while Duty(SCK) = 50%.

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