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STM32F479AI Datasheet(PDF) 180 Page - STMicroelectronics

Part # STM32F479AI
Description  8- to 14-bit parallel camera interface up to 54 Mbytes
PDF  208 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F479AI Datasheet(HTML) 180 Page - STMicroelectronics

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Electrical characteristics
STM32F479xx
180/208
DocID028010 Rev 2
Table 105. SDRAM write timings(1)
1. Guaranteed based on test during characterization.
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
ns
td(SDCLKL _Data)
Data output valid time
-
2.5
th(SDCLKL _Data)
Data output hold time
3.5
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL_SDNWE)
SDNWE valid time
-
1
th(SDCLKL_SDNWE)
SDNWE hold time
0
-
td(SDCLKL_ SDNE)
Chip select valid time
-
0.5
th(SDCLKL-_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
2
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
0.5
td(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
td(SDCLKL_NBL)
NBL valid time
-
0.5
th(SDCLKL_NBL)
NBL output time
0
-
Table 106. LPSDR SDRAM write timings(1)
1. Guaranteed based on test during characterization.
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
ns
td(SDCLKL _Data)
Data output valid time
-
5
th(SDCLKL _Data)
Data output hold time
2
-
td(SDCLKL_Add)
Address valid time
-
2.8
td(SDCLKL-SDNWE)
SDNWE valid time
-
2
th(SDCLKL-SDNWE)
SDNWE hold time
1
-
td(SDCLKL- SDNE)
Chip select valid time
-
1.5
th(SDCLKL- SDNE)
Chip select hold time
1
-
td(SDCLKL-SDNRAS)
SDNRAS valid time
-
1.5
th(SDCLKL-SDNRAS)
SDNRAS hold time
1.5
-
td(SDCLKL-SDNCAS)
SDNCAS valid time
-
1.5
td(SDCLKL-SDNCAS)
SDNCAS hold time
1.5
-
td(SDCLKL_NBL)
NBL valid time
-
1.5
th(SDCLKL-NBL)
NBL output time
1.5
-



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