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PC87413 Datasheet(PDF) 253 Page - National Semiconductor (TI) |
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PC87413 Datasheet(HTML) 253 Page - National Semiconductor (TI) |
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253 / 257 page  11.0 Device Characteristics (Continued) Revision 1.2 253 www.national.com 11.5.10 SWC Timing Inputs at VSB Power Switching Figure 67. Inputs at VSB Power Switching (No VBAT) Symbol Figure Description Reference Conditions Min Max tEWIV 67 External Wake-up inputs valid1 1. Not tested. Guaranteed by design. At VSB power On, after the 32 KHz clock is stable2 2. No VBAT; the 32 KHz internal clock is stopped while VSB is Off (see Low Frequency Clock Timing on page 242). 1 s 1.25 s tPBOP 68 PWBTOUT pulse time1 Resume by SLPS3, SLPS5 after Power Fail 100 ms3, 3. Except when generated by PWBTIN pulse. 100.03 ms VSB (Power) RI1, RI2 GPIOE10-17, tEWIV GPIOE40-47 KBCLK, MCLK VSBOFF VSBON KBDAT, MDAT (Internal) VSB Power-Up Reset 32 KHz Clock (internal) t32KW tIRST PWBTIN, SLBTIN XIRQ SLPS3, SLPS5 |
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