PC87413 datasheet(141/257 Pages) NSC

141 / 257 page

7.0 General-Purpose Input/Output (GPIO) Ports (Continued)

Revision 1.2

141

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7.4.5

GPIO Event Enable Register (GPEVEN)

Power Well:VSB

Location:Device specific

Type:

R/W

7.4.6

GPIO Event Status Register (GPEVST)

Power Well:VSB

Location:Device specific

Type:

R/W1C

Bit

76543210

Name

EVTENA

Reset

00000000

Bit

Description

7-0

EVTENA (Event Enable). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. Each bit enables system

notiﬁcation by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPEVST

0: Event Pending by corresponding GPIO pin masked

1: Event Pending by corresponding GPIO pin enabled

Bit

76543210

Name

EVTSTAT

Reset

00000000

Bit

Description

7-0

EVTSTAT (Event Status). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. The setting of each bit is

independent of the Event Enable bit in the GPEVEN register. An active event sets the Status bit, which may be

cleared only by software writing 1 to the bit.

0: No active edge or level detected since last cleared

1: Active edge or level detected

PC87413 Datasheet(PDF) 141 Page - National Semiconductor (TI)

PC87413 Datasheet(HTML) 141 Page - National Semiconductor (TI)

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