TMS320C6472ECTZ datasheet(195/269 Pages) TI1

195 / 269 page

TMS320C6472

www.ti.com

SPRS612G

– JUNE 2009 – REVISED JULY 2011

Table 7-66. DMATCU Transmit Channels 0-5 Registers (continued)

HEX ADDRESS RANGE

ACRONYM

0250 116C

DXCH_BFCNT5

Transmit Channel 5 Frame Count Register B

0250 1170 - 0250 117C

Reserved

Table 7-67. DMATCU Receive Channels 0-5 Registers

HEX ADDRESS RANGE

ACRONYM

0250 1800

DRCH_ABASE0

Receive Channel 0 Memory Base Address Register A

0250 1804

DRCH_AFALLOC0

Receive Channel 0 Frame Allocation Register A

0250 1808

DRCH_AFSIZE0

Receive Channel 0 Frame Size Register A

0250 180C

DRCH_AFCNT0

Receive Channel 0 Frame Count Register A

0250 1810 - 0250 181C

Reserved

0250 1820

DRCH_BBASE0

Receive Channel 0 Memory Base Address Register B

0250 1824

DRCH_BFALLOC0

Receive Channel 0 Frame Allocation Register B

0250 1828

DRCH _BFSIZE0

Receive Channel 0 Frame Size Register B

0250 182C

DRCH _BFCNT0

Receive Channel 0 Frame Count Register B

0250 1830 - 0250 183C

Reserved

0250 1840

DRCH_ABASE1

Receive Channel 1 Memory Base Address Register A

0250 1844

DRCH_AFALLOC1

Receive Channel 1 Frame Allocation Register A

0250 1848

DRCH_AFSIZE1

Receive Channel 1 Frame Size Register A

0250 184C

DRCH_AFCNT1

Receive Channel 1 Frame Count Register A

0250 1850 - 0250 185C

Reserved

0250 1860

DRCH_BBASE1

Receive Channel 1 Memory Base Address Register B

0250 1864

DRCH_BFALLOC1

Receive Channel 1 Frame Allocation Register B

0250 1868

DRCH _BFSIZE1

Receive Channel 1 Frame Size Register B

0250 186C

DRCH _BFCNT1

Receive Channel 1 Frame Count Register B

0250 1870 - 0250 187C

Reserved

0250 1880

DRCH_ABASE2

Receive Channel 2 Memory Base Address Register A

0250 1884

DRCH_AFALLOC2

Receive Channel 2 Frame Allocation Register A

0250 1888

DRCH_AFSIZE2

Receive Channel 2 Frame Size Register A

0250 188C

DRCH_AFCNT2

Receive Channel 2 Frame Count Register A

0250 1890 - 0250 189C

Reserved

0250 18A0

DRCH_BBASE2

Receive Channel 2 Memory Base Address Register B

0250 18A4

DRCH_BFALLOC2

Receive Channel 2 Frame Allocation Register B

0250 18A8

DRCH _BFSIZE2

Receive Channel 2 Frame Size Register B

0250 18AC

DRCH _BFCNT2

Receive Channel 2 Frame Count Register B

0250 18B0 - 0250 18BC

Reserved

0250 18C0

DRCH_ABASE3

Receive Channel 3 Memory Base Address Register A

0250 18C4

DRCH_AFALLOC3

Receive Channel 3 Frame Allocation Register A

0250 18C8

DRCH_AFSIZE3

Receive Channel 3 Frame Size Register A

0250 18CC

DRCH_AFCNT3

Receive Channel 3 Frame Count Register A

0250 18D0 - 0250 18DC

Reserved

0250 18E0

DRCH_BBASE3

Receive Channel 3 Memory Base Address Register B

0250 18E4

DRCH_BFALLOC3

Receive Channel 3 Frame Allocation Register B

0250 18E8

DRCH _BFSIZE3

Receive Channel 3 Frame Size Register B

0250 18EC

DRCH _BFCNT3

Receive Channel 3 Frame Count Register B

0250 18F0 - 0250 18FC

Reserved

0250 1900

DRCH_ABASE4

Receive Channel 4 Memory Base Address Register A

0250 1904

DRCH_AFALLOC4

Receive Channel 4 Frame Allocation Register A

C64x+ Peripheral Information and Electrical Specifications

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