TMS320C6472ECTZ datasheet(215/269 Pages) TI1

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ts127-2

ts127-0

ts127-1

ts000-7

ts000-6

ts000-1

ts000-3

ts000-5

ts000-4

ts000-2

ts000-0

CLKA/B

FSA/B

TRn

(A)

TXn

(A)

ts127-2

ts000-3

ts000-7

ts127-1

ts127-0

ts000-5

ts000-6

ts000-4

ts000-0

ts000-2

ts000-1

TMS320C6472

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SPRS612G

– JUNE 2009 – REVISED JULY 2011

Table 7-99. Timing Requirements for TSIP 1X Mode(1)

(see Figure 7-46)

500/625/700

NO.

UNIT

MIN

MAX

tc(CLK)

Cycle time, CLK rising edge to next CLK rising edge

122.1(2)

tw(CLKL)

Pulse duration, CLK low

0.4 tc(clk)

tw(CLKH)

Pulse duration, CLK high

0.4 tc(clk)

tt(CLK)

Transition time, CLK high to low or CLK low to high

tsu(FS-CLK)

Setup time, fs valid before rising CLK

th(CLK-FS)

Hold time, fs valid after rising CLK

tsu(TR-CLK)

Setup time, tr valid before falling CLK

th(CLK-TR)

Hold time, tr valid before falling CLK

td(CLKH-TX)

Delay time, CLK high to TX valid (1024(2) clock cycles plus)

tdis(CLKH-TXZ)

Disable time, CLK high to TX tristate

(1)

Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 0b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 1. If the polarity

of any of the signals is inverted, then the timing references of that signal are also inverted.

(2)

Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 61 ns and 30.5 ns, respectively.

Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through

255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and

frame sync signals would require a RCVDATD=1023 and a XMTDATD=1023.

Figure 7-46. TSIP 1x Timing Diagram

C64x+ Peripheral Information and Electrical Specifications

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