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TMS320C6472ECTZ Datasheet(PDF) 245 Page - Texas Instruments |
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TMS320C6472ECTZ Datasheet(HTML) 245 Page - Texas Instruments |
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245 / 269 page ![]() UXCLK URCLK (inputs) 1 4 4 2 3 TMS320C6472 www.ti.com SPRS612G – JUNE 2009 – REVISED JULY 2011 7.17.3 UTOPIA Electrical Data/Timing Table 7-145. Timing Requirements for UTOPIA Receive/Transmit Clock (UCLK)(1) (see Figure 7-62) 500/625/700 NO. UNIT MIN MAX 1 tc(UCLK) UXCLK or URCLK cycle time 20 ns 2 tw(UCLKL) UXCLK or URCLK pulse duration low 0.4tc(URCLK) 0.6tc(URCLK) ns 3 tw(UCLKH) UXCLK or URCLK pulse duration high 0.4tc(URCLK) 0.6tc(URCLK) ns 4 tt(UCLK) Transition time, UXCLK or URCLK (high to low or low to high) 2 ns (1) UCLK = UXCLK or URCLK. Figure 7-62. UTOPIA Clock Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 245 Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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