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TMS320C6711 Datasheet(PDF) 103 Page - Texas Instruments |
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TMS320C6711 Datasheet(HTML) 103 Page - Texas Instruments |
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103 / 129 page  TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 103 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 50) [C6711] NO. C6711-100 C6711-150 UNIT NO. MIN MAX UNIT 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5tc(CKRX) − 1 ns 5 t Setup time external FSR high before CLKR low CLKR int 20 ns 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 1 ns 6 t Hold time external FSR high after CLKR low CLKR int 6 ns 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3 ns 7 t Setup time DR valid before CLKR low CLKR int 22 ns 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 3 ns 8 t Hold time DR valid after CLKR low CLKR int 3 ns 8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4 ns 10 t Setup time external FSX high before CLKX low CLKX int 23 ns 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 1 ns 11 t Hold time external FSX high after CLKX low CLKX int 6 ns 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3 ns timing requirements for McBSP†‡ (see Figure 50) [C6711B] NO. C6711B-100 C6711B-150 C6711BGFNA-100 UNIT MIN MAX 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5tc(CKRX) − 1 ns 5 t Setup time external FSR high before CLKR low CLKR int 20 ns 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 1 ns 6 t Hold time external FSR high after CLKR low CLKR int 6 ns 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 5 ns 7 t Setup time DR valid before CLKR low CLKR int 22 ns 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 3 ns 8 t Hold time DR valid after CLKR low CLKR int 3 ns 8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 5 ns 10 t Setup time external FSX high before CLKX low CLKX int 23 ns 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 1 ns 11 t Hold time external FSX high after CLKX low CLKX int 6 ns 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3 ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. § The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP and other device is 75 Mbps for 150 MHz CPU clock or 50 Mbps for 100 MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 33 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. |
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