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Integrated Functions (Continued)

CVSP

CRT Vertical Sync Polarity:

0 = Causes CRT VSYNC signal to be normally low, generating a high pulse during the retrace interval.

1 = Cause CRT VSYNC signal to be normally high, generating a low pulse during the retrace interval.

CHSP

CRT Horizontal Sync Polarity:

0 = Causes CRT HSYNC signal to be normally low, generating a high pulse during the retrace interval.

1 = Causes CRT HSYNC signal to be normally high, generating a low pulse during the retrace interval.

7BLNK

Blink Enable: Blink circuitry: 0 = Disable; 1 = Enable.

If enabled, the hardware cursor will blink as well as any pixels. This is provided to maintain compatibility

with VGA text modes. The blink rate is determined by the bit 16 (BKRT).

6VIEN

Vertical Interrupt Enable: Generate a vertical interrupt on the occurrence of the next vertical sync pulse:

0 = Disable, vertical interrupt is cleared;

1 = Enable.

This bit is provided to maintain backward compatibility with the VGA.

5TGEN

Timing Generator Enable: Allow timing generator to generate the timing control signals for the display.

0 = Disable, the Timing Registers may be reprogrammed, and all circuitry operating on the DOTCLK will be

reset.

1 = Enable, no write operations are permitted to the Timing Registers.

DDCK

DDC Clock: This bit is used to provide the serial clock for reading the DDC data pin. This bit is multiplexed

onto the CRTVSYNC pin, but in order for it to have an effect, the VSYE bit must be set low to disable the

normal vertical sync. Software should then pulse this bit high and low to clock data into the GXm proces-

sor.

This feature is provided to allow support for the VESA Display Data Channel standard level DDC1.

3BLKE

Blank Enable: Allow generation of the composite blank signal to the display device:

0 = Disable; 1 = Enable.

When disabled, the BLANK# output will be a static low level. This allows VESA DPMS compliance.

2VSYE

Horizontal Sync Enable: Allow generation of the horizontal sync signal to a CRT display device:

0 = Disable; 1 = Enable.

When disabled, the HSYNC output will be a static low level. This allows VESA DPMS compliance.

Note that this bit only applies to the CRT; the flat panel HSYNC is controlled by the automatic power

sequencing logic.

HSYE

Vertical Sync Enable: Allow generation of the vertical sync signal to a CRT display device:

0 = Disable; 1 = Enable.

When disabled, the VSYNC output will be a static low level. This allows VESA DPMS compliance.

Note that this bit only applies to the CRT; the flat panel VSYNC is controlled by the automatic power

sequencing logic.

0FPPE

Flat Panel Power Enable: On a low-to-high transition this bit will enable the flat panel power-up sequence

to begin. This will first turn on VDD to the panel, then start the clocks, syncs, and pixel bus, then turn on

the LCD bias voltage, and finally the backlight.

On a high-to-low transition, this bit will disable the outputs in the reverse order.

GX_BASE+830Ch-830Fh

DC_OUTPUT_CFG Register (R/W)

Default Value = xxx00000h

31:16

RSVD

Reserved: Set to 0.

DIAG

Compressed Line Buffer Diagnostic Mode: This bit will allow testability of the Compressed Line Buffer

via the diagnostic access registers. A low-to-high transition will reset the Compressed Line Buffer write

pointer. 0 = Disable (Normal operation); 1 = Enable.

CFRW

Compressed Line Buffer Read/Write Select: Enables the read/write address to the Compressed Line

Buffer for use in diagnostic testing of the RAM.

0 = Write address enabled

1 = Read address enabled

PDEH

Panel Data Enable High:

0 = The PANEL[17:9] data bus to be driven to a logic low level to effectively blank an attached flat panel

display or disable the upper pixel data bus for 16-bit pixel port RAMDACs.

1 = If no flat panel is attached, the PANEL[17:9] data bus will be driven with active pixel data. If a flat panel

is attached, setting this bit high will have no effect

− the upper panel bus will be driven based upon the

power sequencing logic.

Table 4-30. Display Controller Configuration and Status Registers (Continued)

Bit

Name

Description

GXM Datasheet(PDF) 142 Page - National Semiconductor (TI)

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