ST92185B datasheet(130/178 Pages) STMICROELECTRONICS

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ST92185B - ON SCREEN DISPLAY (OSD)

ON SCREEN DISPLAY (Cont’d)

DISPLAY

CONTROL

MODE

(DCM1R)

R251 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = Reserved bits, keep in reset state.

Bit 3 = EXTF:

External Font.

Only when the emulator is used, this bit selects the

font memory containing a user-defined OSD font.

In normal user application, this bit has no effect.

0: Internal font memory of the emulator chip.

1: External font RAM of the emulator board.

Bit 2 = FBL:

Fast Blanking Active Level control bit.

The FBL bit must be reset if the on-screen display

is done while the FB output is low. The FBL bit

must be set if the on-screen display is done while

the FB output is high. This bit also controls the

TSLU AF output polarity with the same rule as for

FB.

Bit 1 = PM:

Line Mode control bit.

If PM is reset, the display is working in Full page

mode, i.e. the screen is composed of one header,

23 text rows plus 2 status rows. If PM is set, the

display works in Line mode.

Line mode allows up to 12 rows to be displayed

anywhere on the screen. The row attribute (see

TDSRAM mapping) contains the row numbers on

the screen. The byte position of the row attribute

conrresponds to the row in the TDSRAM. For ex-

ample, if the 3rd byte of the row attribute contains

6, the 3rd row in TDSRAM will be displayed as the

6th row on the screen.

Bit 0 = SPM:

Serial/Parallel Mode control bit.

If the SPM bit is reset, the display is done in Serial

mode, i.e. a character or attribute is coded with a

single byte. If the SPM bit is set, the display is

done in Parallel mode, i.e. a character or an at-

tribute is coded on two bytes.

TDSRAM POINTER REGISTER (TDPR)

R252 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = HS[3:0]: Location of the current Header

and Status Rows in the TDSRAM.

Bit 3:0 = PG[3:0]: Location of the current Page

content (rows 1 to 23) in the TDSRAM. For more

details, refer to Section .

The HS[3:0] and PG[3:0] bits described by the

R246 and R247 registers in page 32. Display loca-

tions, Head/Stat location, Page location, are phys-

ically the same: these sets of address bits can be

modified through two different programming ac-

cesses.

0000

EXTF

FBL

SPM

HS3

HS2

HS1

HS0

PG3

PG2

PG1

PG0

ST92185B Datasheet(PDF) 130 Page - STMicroelectronics

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