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ST92185B Datasheet(PDF) 136 Page - STMicroelectronics |
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ST92185B Datasheet(HTML) 136 Page - STMicroelectronics |
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136 / 178 page  136/178 ST92185B - SYNC CONTROLLER 7.5 SYNC CONTROLLER The SYNC Controller receives Horizontal / Vertical sync information coming from the chassis. The VSYNC and HSYNC inputs use schmitt triggers to guarantee sufficient noise rejection. The SYNC Controller unit provides the H internal sync signal to the Display Skew Corrector, which rephases the Pixel clock. It provides also the H and V internal sync signals to the TDSRAM Controller to perform correct TV line counting, thus generating the necessary time windows for a proper TDSRAM access real time sharing by the Display Controller and the CPU (for more details refer to the TDSRAM Controller chap- ter). Field information is also available for the Dis- play Controller. The SYNC Controller unit also generates two in- terrupt sources corresponding respectively the TV field start and to the end of VBI event (“VBI” stands for Vertical Blank Interval). The SYNC Controller implements also a “Compos- ite Sync” signal generator which provides a com- posite sync output signal (called CSO) available through an I/O port alternate function. Figure 83. Sync Controller Block Diagram n Hout 1 0 1 0 pgmble delay HSF(3:0) line counter EOFVBI interrupt Vout HFLG Pulse shaper EOFVBI FLDST FLDEV MOD0 MOD1 HSF(3:0) VPOL HPOL SCCS0 Register SCCS1R Register FSTEN VSEP VDLY VBIEN Skew Corrector Hint Field detect. FLDEV Vout Vout FLDST interrupt Pulse shaper (to DISPLAY, etc.) (to DISPLAY, etc.) VSYNC VPOL VSEP Vertical Sync Extr. VDLY HSYNC HPOL CSYNC Hpls CSO_AF VPOL Field MOD1 MOD0 4 MHz (from Sync Ext.) MOD1 Hpls Equalization Pulse Vertical Pulse Generator & Line Sequencer (MOD0+MOD1)*VSEP Vertical Controller MOD0 Internal H generator (64 µs) Composite Sync. Generator Vcso VR02092A |
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