ST92185B datasheet(141/178 Pages) STMICROELECTRONICS

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ST92185B - SYNC CONTROLLER

SYNC CONTROLLER (Cont’d)

SYNC CONTROLLER CONTROL AND STATUS

R243 - Read/Write

Reset value: 0000 0000 (00h)

Bit 7= EOFVBI:

End Of VBI Flag.

This bit is set to “1” by hardware at the beginning

of the line 25 of the current field, when the End of

VBI interrupt request is sent to the Core. The

EOFVBI flag must be reset by software before the

end of the current field.

Bit 6= FLDST:

Field Start Flag.

This bit is set to “1” by hardware on the leading

edge of the vertical sync pulse when the field start

interrupt request is forwarded to the Core. The

FLDST flag must be reset by software before the

end of the current field.

Bit 5= FLDEV:

Field Even Flag.

This bit is read-only. It indicates which field is cur-

rently running;

0: First field is running

1: Second field is running

Bit 4= HFLG:

Horizontal Sync Flag.

This bit is read-only. It just copies the Horizontal

sync transient information issued by the horizontal

pulse shape unit. The bit is read at “1” at during

each H sync pulse and lasts to “1” up to 4 µs.

Bit 3= FSTEN:

Field Start Interrupt Enable.

0: The FLDST interrupt is disabled and the exter-

nal interrupt pin becomes the interrupt input.

1: The FLDST interrupt is enabled and the inter-

rupt from the external pin is disabled.

Bit 2= VBIEN:

VBI Interrupt Enable.

0: The EOFVBI interrupt is disabled and the exter-

nal interrupt pin becomes the interrupt input.

1: The EOFVBI interrupt is enabled and the inter-

rupt from the external pin is disabled.

Bit 1:0= MOD[1:0]:

EOFVBI FLDST FLDEV HFLG FSTEN VBIEN MOD1 MOD0

MOD1 MOD0 H & V sync

sources

CSO

CSO generator

chassis

sync pulses

reserved

from Xtal

(60 Hz)

yes

on-chip timing genera-

tor; free-running

from Xtal

(50 Hz)

yes

on-chip timing genera-

tor; free-running

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