STM32F303XD datasheet(101/173 Pages) STMICROELECTRONICS

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STM32F303xD STM32F303xE

Electrical characteristics

151

Synchronous waveforms and timings

Figure 24 and Figure 27 present the synchronous waveforms and Table 53 to Table 56

provide the corresponding timings. The results shown in these tables are obtained with the

following FSMC configuration:

•

BurstAccessMode = FMC_BurstAccessMode_Enable;

•

MemoryType = FMC_MemoryType_CRAM;

•

WriteBurst = FMC_WriteBurst_Enable;

•

CLKDivision = 1;

•

DataLatency = 2 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, the THCLK is the HCLK clock period (with maximum FMC_CLK =

36 MHz).

Table 51. Asynchronous multiplexed PSRAM/NOR write timings(1)

1. Based on characterization, not tested in production.

Symbol

Parameter

Min

Max

Unit

tw(NE)

FMC_NE low time

4THCLK-1

4THCLK+1

tv(NWE_NE)

FMC_NEx low to FMC_NWE low

THCLK

THCLK+0.5

tw(NWE)

FMC_NWE low time

2THCLK-0.5

2THCLK+1

th(NE_NWE)

FMC_NWE high to FMC_NE high hold

time

THCLK-0.5

tv(A_NE)

FMC_NEx low to FMC_A valid

tv(NADV_NE)

FMC_NEx low to FMC_NADV low

2.5

tw(NADV)

FMC_NADV low time

THCLK-2

THCLK+2

th(AD_NADV)

FMC_AD(adress) valid hold time after

FMC_NADV high)

THCLK-2

th(A_NWE)

Address hold time after FMC_NWE high

THCLK-1

th(BL_NWE)

FMC_BL hold time after FMC_NWE high

THCLK-0.5

tv(BL_NE)

FMC_NEx low to FMC_BL valid

tv(Data_NADV)

FMC_NADV high to Data valid

THCLK +3.5

th(Data_NWE)

Data hold time after FMC_NWE high

THCLK +0.5

Table 52. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)

1. Based on characterization, not tested in production.

Symbol

Parameter

Min

Max

Unit

tw(NE)

FMC_NE low time

9THCLK

9THCLK+0.5

tw(NWE)

FMC_NWE low time

6THCLK

6THCLK+2

tsu(NWAIT_NE)

FMC_NWAIT valid before FMC_NEx high

5THCLK+6

th(NE_NWAIT)

FMC_NEx hold time after FMC_NWAIT

invalid

5THCLK-5

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