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STM32F303XD Datasheet(PDF) 146 Page - STMicroelectronics |
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STM32F303XD Datasheet(HTML) 146 Page - STMicroelectronics |
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146 / 173 page ![]() Electrical characteristics STM32F303xD STM32F303xE 146/173 DocID026415 Rev 5 Figure 52. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.21 Comparator characteristics 2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is involved. 3. Data based on characterization results, not tested in production. Table 87. Comparator characteristics(1) Symbol Parameter Conditions Min. Typ. Max. Unit VDDA Analog supply voltage - 2 - 3.6 V VIN Comparator input voltage range -0 - VDDA VBG Scaler input voltage - - VREFINIT - VSC Scaler offset voltage - - ±5 ±10 mV tS_SC Scaler startup time from power down -- - 0.2 ms tSTART Comparator startup time VDDA ≥ 2.7 V - - 4 µs VDDA < 2.7 V - - 10 tD Propagation delay for 200 mV step with 100 mV overdrive VDDA ≥ 2.7 V - 25 28 ns VDDA < 2.7 V - 28 30 Propagation delay for full range step with 100 mV overdrive VDDA ≥ 2.7 V - 32 35 VDDA < 2.7 V - 35 40 VOFFSET Comparator offset error VDDA ≥ 2.7 V - ±5 ±10 mV VDDA < 2.7 V - - ±25 |
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