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LAN91C111 Datasheet(PDF) 116 Page - Microchip Technology

Part # LAN91C111
Description  10/100 Non-PCI Ethernet Single Chip MAC PHY
PDF  125 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN91C111 Datasheet(HTML) 116 Page - Microchip Technology

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 2011-2016 Microchip Technology Inc.
DS00002276A-page 117
LAN91C111
TABLE 14-4:
LINK PULSE TIMING CHARACTERISTICS
SYM
Parameter
Limit
Unit
Condition
MIN
TYP
MAX
t42
NLP Transmit Link Pulse Width
See Figure 7-8
nS
t43
NLP Transmit Link Pulse Period
8
24
mS
t44
NLP Receive Link Pulse Width Required
For Detection
50
nS
t45
NLP Receive Link Pulse Minimum Period
Required For Detection
6
7
mS
link_test_min
t46
NLP Receive Link Pulse Maximum
Period Required For Detection
50
150
mS
link_test_max
t47
NLP Receive Link Pulse Required To
Exit Link Fail State
33
3Link
Pulses
lc_max
t48
FLP Transmit Link Pulse Width
100
150
nS
t49
FLP Transmit Clock Pulse to Data Pulse
Period
55.5
62.5
69.5
S
interval_timer
t50
FLP Transmit Clock Pulse to Clock Pulse
Period
111
125
139
S
t51
FLP Transmit Link Pulse Burst Period
8
22
mS
transmit_link_burst_time
r
t52
FLP Receive Link Pulse Width Required
For Detection
50
nS
t53
FLP Receive Link Pulse Minimum Period
Required For Clock Pulse Detection
525
S
flp_test_min_timer
t54
FLP Receive Link Pulse Maximum
Period Required For Clock Pulse
Detection
165
185
S
flp_test_max_timer
t55
FLP Receive Link Pulse Minimum Period
Required For Data Pulse Detection
15
47
S
data_detect_min_timer
t56
FLP Receive Link Pulse Maximum
Period Required For Data Pulse
Detection
78
100
S
data_detect_max_timer
t57
FLP Receive Link Pulse Burst Minimum
Period Required For Detection
5
7
mS
nlp_test_min_timer
t58
FLP Receive Link Pulse Burst Maximum
Period Required For Detection
50
150
mS
nlp_test_max_timer
t59
FLP Receive Link Pulses Bursts
Required To Detect Auto-Negotiation
Capability
33
3Link
Pulses



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