LAN91C111 datasheet(121/125 Pages) MICROCHIP

121 / 125 page

LAN91C111

DS00002276A-page 120

 2011-2016 Microchip Technology Inc.

APPENDIX A:

DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

REVISION LEVEL & DATE

SECTION/FIGURE/ENTRY

CORRECTION

DS00002276A (09-01-16)

Replaces previous SMSC version Rev. 1.92 (06-27-11)

Rev. 1.92 (06-27-11)

Section 7.7.17, "PHY

Powerdown," on page 36

Added note stating that the PDN bit must not be

set when the device is in external PHY mode.

Table 10-1, “Typical Flow Of

Events For Placing Device

In Low Power Mode,” on

page 77

Added note to step 6 stating that the bit (PDN)

must not be set when the device is in external PHY

mode.

Table 10-2, “Flow Of Events

For Restoring Device In

Normal Power Mode,” on

page 78

Added note to step 3 stating that the step is only

performed when the device is in internal PHY

mode.

Table 9.1, “Register 0.

Control Register,” on

page 69

Added note to PDN bit definition stating that the bit

must not be set when the device is in external PHY

mode.

Rev. 1.91 (06-01-09)

The following ordering information has been removed: “LAN91C111-NC,

LAN91C111i-NC (Industrial Temperature) for 128 pin QFP packages”,

“LAN91C111-NE, LAN91C111i-NE (Industrial Temperature) for 128-pin TQFP

packages” as these has been discontinued.

All

Updated document references to Rev. C.

Section 13.1, "Maximum

Ratings*," on page 97

Fixed commercial temp range to state “0

C to

+70

C for LAN91C111”

Cover

Added bullet: “Commercial Temperature Range

from 0

C to 70C (LAN91C111)”

Section 8.24, "Bank 3 -

Revision Register," on

page 62

Changed REV default from “0001” to “0010”

Table 14-3, “Asynchronous

Cycle - nADS=0,” on

page 104

Changed T1A time in table under figure from 10nS

min to 2nS min.

Section 10.4, "Typical Flow

of Event For Receive," on

page 80

In step 4, changed last sentence from “If CRC is

incorrect the packet memory is released and no

interrupt will occur.”, to “The RCV_BAD bit of the

Bank 1 Control Register controls whether or not to

generate interrupts when bad CRC packets are

received.”

Section 7.7.14, "Receive

Polarity Correction," on

page 35

Added note at end of 10 Mbps subsection stating

“The first 3 received packets must be discarded

after the correction of a reverse polarity condition.”

LAN91C111 Datasheet(PDF) 121 Page - Microchip Technology

LAN91C111 Datasheet(HTML) 121 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL