STM32F413RHT6 datasheet(122/207 Pages) STMICROELECTRONICS

122 / 207 page

Electrical characteristics

STM32F413xG/H

122/207

DocID029162 Rev 2

Static latchup

Two complementary static tests are required on six parts to assess the latchup

performance:

•

A supply overvoltage is applied to each power supply pin

•

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

6.3.15

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or

above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product

operation. However, in order to give an indication of the robustness of the microcontroller in

cases when abnormal injection accidentally happens, susceptibility tests are performed on a

sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins

(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator

frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced

leakage current by positive injection.

The test results are given in Table 57.

Table 55. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Maximum

value(1)

Unit

VESD(HBM)

Electrostatic

discharge voltage

(human body model)

TA = +25 °C conforming to JESD22-A114

2000

VESD(CDM)

Electrostatic

discharge voltage

(charge device model)

TA = +25 °C conforming to ANSI/ESD STM5.3.1,

UFBGA144, UFBGA100, LQFP144, LQFP100,

WLCSP81, LQFP64

3250

TA = +25 °C conforming to ANSI/ESD STM5.3.1,

UFQFPN48

4500

1. Guaranteed by characterization.

Table 56. Electrical sensitivities

Symbol

Parameter

Conditions

Class

Static latch-up class

TA = +125 °C conforming to JESD78A

II level A

STM32F413RHT6 Datasheet(PDF) 122 Page - STMicroelectronics

STM32F413RHT6 Datasheet(HTML) 122 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL