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MB91F577CSPMC Datasheet(PDF) 130 Page - Cypress Semiconductor |
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MB91F577CSPMC Datasheet(HTML) 130 Page - Cypress Semiconductor |
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130 / 163 page ![]() Document Number: 002-04725 Rev.*A Page 130 of 163 MB91570 Series 13.4.5.3 I 2C timing (TA: Recommended operating conditions, VCC5 = 5.0V±10%, VSS = AVSS = 0.0V) Parameter Symbol Pin name Conditions Standard mode High-speed mode Unit Remark s Min Max Min Max SCL clock frequency fSCL SCK0_0, SCK1_0 CL = 50 pF (When drive capability is 2mA or more.) CL=20pF (When drive capability is 1mA) R = (VP/IOL) * 1 0 100 0 400 kHz Repeat "start" condition hold time SDA ↓→ SCL ↓ tHDSTA SOT0_0, SOT1_0 (SDA) SCK0_0,SCK1_0 (SCL) 4.0 – 0.6 – µs Width of "L" for SCL clock tLOW SCK0_0, SCK1_0 (SCL) 4.7 – 1.3 – µs Width of "H" for SCL clock tHIGH SCK0_0, SCK1_0 (SCL) 4.0 – 0.6 – µs Repeat "start" condition setup time SCL ↑→ SDA ↓ tSUSTA SCK0_0, SCK1_0 (SCL) 4.7 – 0.6 – µs Data hold time SCL ↓→ SDA ↓↑ tHDDAT SOT0_0, SOT1_0 (SDA) SCK0_0, SCK1_0 (SCL) 0 3.45 *2 0 0.9 µs Data setup time SDA ↓↑→ SCL ↑ tSUDAT SOT0_0, SOT1_0 (SDA) SCK0_0, SCK1_0 (SCL) 250 *3 – 100 – ns "Stop" condition setup time SCL ↑ →SDA ↑ tSUSTO SOT0_0, SOT1_0 (SDA) SCK0_0, SCK1_0 (SCL) 4.0 – 0.6 – µs Bus-free time between "stop" condition and "start" condition tBUF – 4.7 – 1.3 – µs Noise filter tSP – – 2tCPP *4 – 2tCPP *4 – ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines, respectively. VP shows the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current. *2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal. *3: A high-speed mode I 2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCPP is the peripheral clock cycle time. Adjust the peripheral bus clock to 8MHz or more when use I 2C. |
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