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TNETV2664FIBZWT Datasheet(PDF) 193 Page - Texas Instruments |
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TNETV2664FIBZWT Datasheet(HTML) 193 Page - Texas Instruments |
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193 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 6.13 Multichannel Buffered Serial Port (McBSP) The McBSP provides these functions: • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices • External shift clock or an internal, programmable frequency shift clock for data transfer If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater. For more detailed information on the McBSP peripheral, see the TMS320C642x DSP Multichannel Buffered Serial Port (McBSP) User's Guide (literature number SPRUEN2). 6.13.1 McBSP Peripheral Register Description(s) Table 6-38. McBSP 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA3 controller can only read 01D0 0000 DRR0 McBSP0 Data Receive Register this register; they cannot write to it. 01D0 0004 DXR0 McBSP0 Data Transmit Register 01D0 0008 SPCR0 McBSP0 Serial Port Control Register 01D0 000C RCR0 McBSP0 Receive Control Register 01D0 0010 XCR0 McBSP0 Transmit Control Register 01D0 0014 SRGR0 McBSP0 Sample Rate Generator register 01D0 0018 MCR0 McBSP0 Multichannel Control Register McBSP0 Enhanced Receive Channel Enable Register 01D0 001C RCERE00 0 Partition A/B McBSP0 Enhanced Transmit Channel Enable Register 01D0 0020 XCERE00 0 Partition A/B 01D0 0024 PCR0 McBSP0 Pin Control Register McBSP0 Enhanced Receive Channel Enable Register 01D0 0028 RCERE10 1 Partition C/D McBSP0 Enhanced Transmit Channel Enable Register 01D0 002C XCERE10 1 Partition C/D McBSP0 Enhanced Receive Channel Enable Register 01D0 0030 RCERE20 2 Partition E/F McBSP0 Enhanced Transmit Channel Enable Register 01D0 0034 XCERE20 2 Partition E/F McBSP0 Enhanced Receive Channel Enable Register 01D0 0038 RCERE30 3 Partition G/H McBSP0 Enhanced Transmit Channel Enable Register 01D0003C XCERE30 3 Partition G/H 01D0 0040 - 01D0 07FF - Reserved Table 6-39. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA controller can only read 01D0 0800 DRR1 McBSP1 Data Receive Register this register; they cannot write to it. Copyright © 2007–2009, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 193 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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