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TNETV2665FIBZWT7 Datasheet(PDF) 171 Page - Texas Instruments |
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TNETV2665FIBZWT7 Datasheet(HTML) 171 Page - Texas Instruments |
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171 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 6.9 External Memory Interface (EMIF) C6424 supports several memory and external device interfaces, including: • Asynchronous EMIF (EMIFA) for interfacing to NOR Flash, SRAM, etc. • NAND Flash 6.9.1 Asynchronous EMIF (EMIFA) The C6424 Asynchronous EMIF (EMIFA) provides a 16-bit data bus, an address bus width up to 24-bits, and 4 chip selects, along with memory control signals. These signals are multiplexed between these peripherals: • EMIFA and NAND interfaces • EMAC (RMII) • PCI • GPIO 6.9.2 NAND (NAND, SmartMedia, xD) The EMIFA interface provides both the asynchronous EMIF and NAND interfaces. Four chip selects are provided and each are individually configurable to provide either EMIFA or NAND support. The NAND features supported are as follows. • NAND flash on up to 4 asynchronous chip selects. • 8- or 16-bit data bus width • Programmable cycle timings. • Performs ECC calculation. • NAND Mode also supports SmartMedia and xD memory cards • Boot ROM supports booting of the C6424 from NAND flash located at CS2 The memory map for EMIFA and NAND registers is shown in Table 6-23. For more details on the EMIFA and NAND interfaces, the TMS320C642x DSP Peripherals Overview Reference Guide (literature number SPRUEM3) and the TMS320C642x Asynchronous External Memory Interface (EMIF) User's Guide (literature number SPRUEM7). Copyright © 2007–2009, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 171 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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