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TNETV1644ZDU6 Datasheet(PDF) 275 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 275 Page - Texas Instruments |
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275 / 306 page  6.17.2 EMAC Electrical Data/Timing MRCLK 2 3 1 MTCLK 2 3 1 TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 Table 6-85. Timing Requirements for MRCLK (see Figure 6-44) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT 10 Mbps 100 Mbps MIN MAX MIN MAX 1 tc(MRCLK) Cycle time, MRCLK 400 40 ns 2 tw(MRCLKH) Pulse duration, MRCLK high 140 14 ns 3 tw(MRCLKL) Pulse duration, MRCLK low 140 14 ns Figure 6-44. MRCLK Timing (EMAC - Receive) Table 6-86. Timing Requirements for MTCLK (see Figure 6-44) -7/-6/-5/-4 -L/-Q6/-Q5/-Q4 NO. UNIT 10 Mbps 100 Mbps MIN MAX MIN MAX 1 tc(MTCLK) Cycle time, MTCLK 400 40 ns 2 tw(MTCLKH) Pulse duration, MTCLK high 140 14 ns 3 tw(MTCLKL) Pulse duration, MTCLK low 140 14 ns Figure 6-45. MTCLK Timing (EMAC - Transmit) Table 6-87. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-46) -7/-6/-5/-4 -L/-Q6/-Q5/- NO. UNIT Q4 MIN MAX 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns 2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high 8 ns (1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER. Submit Documentation Feedback Peripheral Information and Electrical Specifications 275 |
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