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ST10F296 Datasheet(PDF) 329 Page - STMicroelectronics

Part # ST10F296
Description  High performance 16-bit CPU with DSP functions
PDF  346 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F296 Datasheet(HTML) 329 Page - STMicroelectronics

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ST10F296E
Electrical characteristics
329/346
1
Partially tested, guaranteed by design characterization.
t38 (CC)
ALE falling edge to latched
CS
-4 - tA
6 - tA
-4 - tA
6 - tA
ns
t39 (SR)
Latched CS low to valid data
in
-
16.5 + tC + 2tA
-
3TCL - 21+ tC + 2tA
ns
t41 (CC)
Latched CS hold after RD
and WR
2 + tF
-
TCL - 10.5 + tF
-ns
t82 (CC)
Address setup to RdCS and
WrCS
(with R/W delay)
14 + 2tA
-
2TCL - 11 + 2tA
-ns
t83 (CC)
Address setup to RdCS and
WrCS (no R/W delay)
2 + 2tA
-
TCL - 10.5 + 2tA
-ns
t46 (SR)
RdCS to valid data in
(with R/W delay)
-
4 + tC
-
2TCL - 21 + tC
ns
t47 (SR)
RdCS to valid data in
(no R/W delay)
-
16.5 + tC
-
3TCL - 21 + tC
ns
t48 (CC)
RdCS and WrCS low time
(with RW-delay)
15.5 + tC
-
2TCL - 9.5 + tC
-ns
t49 (CC)
RdCS and WrCS low time
(no R/W delay)
28 + tC
-
3TCL - 9.5 + tC
-ns
t50 (CC)
Data valid to WrCS
10 + tC
-
2TCL - 15 + tC
-ns
t51 (SR)
Data hold after RdCS
0-
0
-
ns
t53 (SR)
Data float after RdCS
(with R/W delay)
-
16.5 + tF
-
2TCL - 8.5 + tF
ns
t68 (SR)
Data float after RdCS
(no R/W delay)
-
4 + tF
-
TCL - 8.5 + tF
ns
t55 (CC)
Address hold after RdCS
and WrCS
-8.5 + tF
-
-8.5 + tF
-ns
t57 (CC)
Data hold after WrCS
2 + tF
-
TCL - 10.5 + tF
-ns
1.
R/W delay and
t
A refer to the next bus cycle.
2.
Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes which occur before the end of RD have no impact on read cycles.
Table 176.
Demultiplexed bus (continued)
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU clock
1/2 TCL = 1 to 64 MHz
Unit
Min
Max
Min
Max
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Product(s)
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