ST72321R7-Auto datasheet(163/243 Pages) STMICROELECTRONICS

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ST72321xx-Auto

I2C bus interface (I2C)

Doc ID 13829 Rev 1

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16.5

Low power modes

16.6

Interrupts

Figure 69.

Interrupt control logic diagram

Note:

The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding Enable Control bit is set and the I-bit in the

CC register is reset (RIM instruction).

Table 81.

Effect of low power modes on I2C

Mode

Effect

Wait

No effect on I2C interface.

I2C interrupts cause the device to exit from Wait mode.

Halt

I2C registers are frozen.

In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus. The

I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from

Halt mode” capability.

Table 82.

I2C interrupt control/wake-up capability

Interrupt event

Event flag

Enable

control bit

Exit from

Wait

Exit from

Halt

10-bit Address Sent Event (Master mode)

ADD10

ITE

Yes

End of Byte Transfer Event

BTF

Address Matched Event (Slave mode)

ADSEL

Start Bit Generation Event (Master mode)

Acknowledge Failure Event

Stop Detection Event (Slave mode)

STOPF

Arbitration Lost Event (Multimaster configuration)

ARLO

Bus Error Event

BERR

BTF

ADSL

STOPF

ARLO

BERR

EVF

INTERRUPT

ITE

* EVF can also be set by EV6 or an error from the SR2 register.

ADD10

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