ST72321R7-Auto datasheet(168/243 Pages) STMICROELECTRONICS

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I2C bus interface (I2C)

ST72321xx-Auto

168/243

Doc ID 13829 Rev 1

16.7.4

I2C clock control register (CCR)

2ARLO

Arbitration lost

This bit is set by hardware when the interface loses the arbitration of the bus to

another master. An interrupt is generated if ITE = 1. It is cleared by software reading

SR2 register or by hardware when the interface is disabled (PE = 0).

After an ARLO event the interface switches back automatically to Slave mode

(M/SL = 0).

The SCL line is not held low while ARLO = 1.

0: No arbitration lost detected

1: Arbitration lost detected

Note: In a Multimaster environment, when the interface is configured in Master

Receive mode it does not perform arbitration during the reception of the

Acknowledge bit. Mishandling of the ARLO bit from the I2CSR2 register may occur

when a second master simultaneously requests the same data from the same slave

and the I2C master does not acknowledge the data. The ARLO bit is then left at 0

instead of being set.

1BERR

Bus error

This bit is set by hardware when the interface detects a misplaced Start or Stop

condition. An interrupt is generated if ITE = 1. It is cleared by software reading SR2

The SCL line is not held low while BERR = 1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Note: If a Bus Error occurs, a Stop or a repeated Start condition should be

generated by the Master to re-synchronize communication, get the transmission

acknowledged and the bus released for further communication.

0GCAL

General Call (Slave mode)

This bit is set by hardware when a general call address is detected on the bus while

ENGC = 1. It is cleared by hardware detecting a Stop condition (STOPF = 1) or

when the interface is disabled (PE = 0).

0: No general call address detected on bus

1: General call address detected on bus

Table 85.

SR2 register description (continued)

Bit

Name

Function

CCR

Reset value: 0000 0000 (00h)

543

FM/SM

CC[6:0]

Table 86.

CCR register description

Bit

Name

Function

7FM/SM

Fast/Standard I2C mode

This bit is set and cleared by software. It is not cleared when the interface is

disabled (PE = 0).

0: Standard I2C mode

1: Fast I2C mode

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