ST72321R7-Auto datasheet(234/243 Pages) STMICROELECTRONICS

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Known limitations

ST72321xx-Auto

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Doc ID 13829 Rev 1

Known limitations

22.1

All Flash and ROM devices

22.1.1

External RC option

The external RC clock source option described in previous datasheet revisions is no longer

supported and has been removed from this specification.

22.1.2

Safe connection of OSC1/OSC2 pins

The OSC1 and/or OSC2 pins must not be left unconnected, otherwise the ST7 main

oscillator may start and, in this configuration, could generate an fOSC clock frequency in

excess of the allowed maximum (> 16 MHz), putting the ST7 in an unsafe/undefined state.

Refer to Section 6.4: Multi-oscillator (MO) on page 38.

22.1.3

Reset pin protection with LVD enabled

As mentioned in Note 2 below Figure 90: RESET pin protection when LVD is enabled on

page 208, when the LVD is enabled, it is recommended not to connect a pull-up resistor or

capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line.

22.1.4

Unexpected reset fetch

If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt

controller does not recognize the source of the interrupt and, by default, passes the RESET

vector address to the CPU.

Workaround

To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction.

22.1.5

External interrupt missed

To avoid any risk of generating a parasitic interrupt, the edge detector is automatically

disabled for one clock cycle during an access to either DDR and OR. Any input signal edge

during this period will not be detected and will not generate an interrupt.

This case can typically occur if the application refreshes the port configuration registers at

intervals during runtime.

Workaround

The workaround is based on software checking the level on the interrupt pin before and after

writing to the PxOR or PxDDR registers. If there is a level change (depending on the

sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction

with three extra PUSH instructions before executing the interrupt routine (this is to make the

call compatible with the IRET instruction at the end of the interrupt service routine).

But detection of the level change does not make sure that edge occurs during the critical 1

cycle duration and the interrupt has been missed. This may lead to occurrence of same

interrupt twice (one hardware and another with software call).

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