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ST72561AR7-Auto Datasheet(PDF) 297 Page - STMicroelectronics

Part # ST72561AR7-Auto
Description  Clock, reset and supply management
PDF  324 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72561AR7-Auto Datasheet(HTML) 297 Page - STMicroelectronics

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ST72561-Auto
Electrical characteristics
Doc ID 12370 Rev 8
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Figure 141. SPI master timing diagram
1.
Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
20.12.2
CAN - controller area network interface
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (CANTX and CANRX).
20.13
10-bit ADC characteristics
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
SS INPUT
CPHA = 0
MOSI OUTPUT
MISO INPUT
CPHA = 0
CPHA = 1
CPHA = 1
tc(SCK)
tw(SCKH)
tw(SCKL)
th(MI)
tsu(MI)
MSB IN
MSB OUT
BIT6 IN
BIT6 OUT
LSB OUT
LSB IN
See note 2
See note 2
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
tr(SCK)
tf(SCK)
th(MO)
tv(MO)
Table 121.
CAN characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tp(RX:TX) CAN controller propagation time
(1)
1.
Data based on characterization results, not tested in production.
-
-
60
ns
Table 122.
ADC characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
fADC
ADC clock frequency
0.4
4
MHz
VAIN
Conversion voltage range(2)
VSSA
VDDA
V



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