## FST2135: 2-Bit Bus Switch with Level Shifter The **FST2135** is a high-speed CMOS 2-bit bus switch. It is primarily used for connecting two buses or as a voltage level translator. It is designed to provide high-speed switching with minimal propagation delay and low "ON" resistance. --- ### 1. Key Technical Specifications | Feature | Description | | :--- | :--- | | **Logic Type** | Bus Switch / Multiplexer | | **Configuration** | 2-Bit (Dual) | | **Supply Voltage ($V_{CC}$)** | 4.0V to 5.5V | | **Input/Output Voltage** | Up to 5.5V | | **Propagation Delay** | < 0.25 ns (almost zero) | | **On-Resistance ($R_{ON}$)** | ~5 $\Omega$ (Typical) | | **Operating Temperature** | -40°C to +85°C | --- ### 2. Functional Characteristics #### A. Zero Propagation Delay Unlike standard buffers, the FST2135 does not use regenerative feedback. It acts as a mechanical switch would, meaning the signal passes through with virtually no delay other than the RC constant of the switch's internal resistance and the load capacitance. #### B. Level Shifting Capability The device is often used for **5V to 3.3V translation**. When the device is powered at 5V, the internal pass transistor limits the output voltage, allowing a 5V input to be safely read by a 3.3V logic device. #### C. Enable/Disable Control The device features an active-low Output Enable (**$\overline{OE}$**) pin. * When **$\overline{OE}$** is LOW: The switch is closed (A is connected to B). * When **$\overline{OE}$** is HIGH: The switch is open (High-Impedance state). --- ### 3. Pinout and Internal Logic While packages may vary (typically MSOP-8 or SOIC-8), the standard pin configuration is as follows: | Pin Name | Function | | :--- | :--- | | **$\overline{OE}$** | Output Enable (Active Low) | | **1A, 2A** | Bus A Inputs/Outputs | | **1B, 2B** | Bus B Inputs/Outputs | | **GND** | Ground | | **$V_{CC}$** | Positive Supply | --- ### 4. Typical Applications 1. **Hot Swapping:** Protecting sensitive components when a peripheral is plugged in while the system is powered. 2. **Voltage Translation:** Interfacing between different logic levels (e.g., legacy 5V sensors and modern 3.3V MCUs). 3. **Bus Isolation:** Cutting off a segment of a bus to reduce capacitive loading or to prevent signal interference. ---