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K32W041AMK Datasheet (PDF) - NXP Semiconductors

K32W041AMK Datasheet PDF - NXP Semiconductors
Part # K32W041AMK
Download  K32W041AMK Download
File Size   1659.43 Kbytes
Page   116 Pages
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors
Description IEEE 802.15.4 and Bluetooth LE 5.0 wireless microcontroller

K32W041AMK Datasheet (PDF)

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K32W041AMK Datasheet PDF - NXP Semiconductors

Part # K32W041AMK
Download  K32W041AMK Click to download

File Size   1659.43 Kbytes
Page   116 Pages
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors
Description IEEE 802.15.4 and Bluetooth LE 5.0 wireless microcontroller

K32W041AMK Datasheet (HTML) - NXP Semiconductors


K32W041AMK Product details

General description
The K32W041A/K32W041AM are ultra-low power, high performance Arm® Cortex®-M4
based wireless microcontrollers supporting Zigbee 3.0, Thread and Bluetooth Low Energy
5.0 networking stacks to facilitate home and building automation, smart lighting, smart
locks and sensor network applications.
The K32W041A/K32W041AM includes a 2.4 GHz Bluetooth Low Energy 5 (supporting
eight simultaneous connections) compliant transceiver, a 2.4 GHz IEEE 802.15.4
compliant transceiver and a comprehensive mix of analog and digital peripherals.
Ultra-low current consumption in both radio receive and transmit modes and also in the
power down modes allow use of coin cell batteries.
The product has 640 KB embedded Flash, 152 KB RAM memory and extend the radio
output power to +15dBm. The K32W041AM has an additional 1 MB Data Flash. The
embedded flash can support Over The Air (OTA) code download to applications. The
devices include a 10-channel PWM, two timers, one RTC/alarm timer, a Windowed
Watchdog Timer (WWDT), two USARTs, two SPI interfaces, two I2C interfaces, a DMIC
subsystem including a dual-channel PDM microphone interface with voice activity
detector, one 12-bit ADC, temperature sensor and a comparator.
The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level support of the block integration. The Arm Cortex-M4 CPU, operates at up to 48 MHz.

Features and benefits
2.1 Benefits
 Very low current solution for long battery life
 Single chip device to run stack and application
 System BOM is low in component count and cost
 Flexible sensor interfacing
 Package
 6x6 mm HVQFN40, 0.5 mm pitch
 Lead-free and RoHS compliant
 Ambient temperature range: 40 C to +85 C
2.2 Radio features
 2.4 GHz IEEE 802.15.4 2011 compliant
 2.4 GHz Bluetooth Low Energy 5.0 compliant
 Receiver current: 7.0 mA
 IEEE 802.15.4 Receiver sensitivity -100 dBm
 Bluetooth Low Energy 5.0 2 Mb/s high data rate
 Bluetooth Low Energy Receiver sensitivity -97 dBm for 1 MB/s
 Improved co-existence with WiFi
 Configurable transmit power up to
 +15 dBm, with 46 dB range
 Transmit power / current
 +15 dBm / 51 mA
 +10 dBm / 26 mA
 +3 dBm /13 mA
 +0 dBm / 10.2 mA
 Supply voltage
 2.4 V to 3.6 V
 Antenna Diversity control
 32 MHz XTAL cell with internal capacitors, able with suitable external XTAL to meet
the required accuracy for radio operation over the operating conditions
 Integrated RF balun
 Integrated ultra Low-power sleep oscillator
 Deep Power-down current (with wake-up on IO)
 350 nA (K32W041A)
 360 nA (K32W041AM)
 128-bit, 192-bit or 256-bit AES security processor
 MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers

Microcontroller features
 Application CPU, Arm Cortex-M4 CPU:
 Arm Cortex-M4 processor, running at a frequency of up to 48 MHz.
 Arm built-in Nested Vectored Interrupt Controller (NVIC)
 Memory Protection Unit (MPU)
 Non-maskable Interrupt (NMI) with a selection of sources
 Serial Wire Debug (SWD) with 8 breakpoints and 4 watchpoints
 System tick timer
 Includes Serial Wire Output for enhanced debug capabilities.
 On-Chip memory
 640 KB flash, K32W041AM has an additional 1 MB data flash
 152 KB SRAM
 12 MHz to 48 MHz system clock speed for low-power
 2 x I2C-bus interface, operate as either master or slave
 10 x PWM on K32W041A and 9 x PWM on K32W041AM
 2 x Low-power timers
 2 x USART, one with flow control
 2 x SPI-bus, master or slave
 1 x PDM digital audio interface with a hardware based voice activity detector to reduce
power consumption in voice applications. Support for dual-channel microphone
interface, flexible decimators, 16 entry FIFOs and optional DC blocking.
 19-channel DMA engine for efficient data transfer between peripherals and SRAM, or
SRAM to SRAM. DMA can operate with fixed or incrementing addresses. Operations
can be chained together to provide complex functionality with low CPU overhead.
 Up to four GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or
both input edges.
 Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR)
combination of input states.
 32-bit Real Time clock (RTC) with 1 s resolution. A timer in the RTC can be used to
wake from Sleep, Deep-sleep and Power-down, with 1 ms resolution
 Voltage Brown Out with 8 programmable thresholds
 8-input (K32W041A) or 5-input (K32W041AM), 12-bit ADC, 190 ksamples/s (Max.).
HW support for continuous operation or single conversions, single or multiple inputs
can be sampled within a sequence. DMA operation can be linked to achieve low
overhead operation.
 1 x analog comparator, for K32W041AM, only one external input can be used to be
compared with the internal reference
 Battery and temperature sensors
 Watchdog timer and POR
 Standby power controller
 Up to 22 (K32W041A) or 18 (K32W041AM) Digital IOs (DIO)
 1 x Quad SPIFI for accessing:
 an external series flash device (K32W041A)
 an internal flash device (K32W041AM)
 Random Number Generator engine
 AES engine AES-128 to 256
 Hash hardware accelerator supporting SHA-1 and SHA-256
 EFuse:
 128-bit random AES key
 Configuration modes
 Trimming
 ISO7816 smart card digital interface which with a suitable external analogue device
can operate as a smart card reader

Low power features
 Sleep mode supported, the CPU in low power state waiting for interrupt
 Deep-sleep mode supported, the CPU in low power state waiting for interrupt, but
extra functionality disabled or in low power state compared to sleep mode
 Power Down mode, main functionality powered down, wakeup possible from IOs,
wakeup possible from some peripherals (I2C, USART, SPI) in a limited function mode
and low power timers
 Deep -power down, very low power state with option of wake-up triggered by IOs, 350
nA for K32W041A device, or 360 nA for K32W041AM device.
 41-bit and 28-bit Low power timers can run in power down mode, clocked by 32 kHz
FRO or 32 kHz XTAL. Timers can run for over one year or 2 days
 Dedicated low power timer, clocked by 32 kHz XTAL, closely integrated with the
Bluetooth Low Energy link layer to maintain the timing reference through power down
cycles




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About NXP Semiconductors


NXP Semiconductors is a publicly traded multinational company that designs, develops, and manufactures a wide range of semiconductors and integrated circuits for various applications, including automotive, industrial, communications, and consumer markets.

The company was founded in 2006 and is headquartered in Eindhoven, Netherlands.

NXP offers a broad portfolio of products, including microcontrollers, microprocessors, secure authentication ICs, power management ICs, RF and microwave components, and sensor solutions, among others.

The company's products are designed to be energy efficient, secure, and reliable, and are used in a variety of applications, including automotive systems, industrial automation and control, smart homes and buildings, and connected devices.

NXP is dedicated to innovation and customer satisfaction, and is committed to providing its customers with the best semiconductor solutions to meet their needs.

*This information is for general informational purposes only, we will not be liable for any loss or damage caused by the above information.




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