FEATURES
■ Access times of 25ns (SRAM) and 120ns (FLASH)
■ Packaging
    • 66 pin, PGA Type, 1.385" square HIP, hermetic ceramic HIP (Package 402)
    • 68 lead, hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height Designed to fi t JEDEC 68 lead 0.990" CQFJ footprint (FIGURE 2). Package to be developed.
■ 128Kx32 SRAM
■ 512Kx32 5V Flash
■ Organized as 128Kx32 of SRAM and 512Kx32 of Flash Memory with common data bus
■ Low power CMOS
■ Commercial, industrial and military temperature ranges
■ TTL compatible inputs and outputs
■ Built-in decoupling caps and multiple ground pins for low noise operation
■ Weight - 13 grams typical

FLASH MEMORY FEATURES
■ 100,000 erase/program cycles minimum
■ Sector architecture
    • 8 equal size sectors of 64KBytes each
    • Any combination of sectors can be concurrently erased. Also supports full chip erase
■ 5V programming; 5V ± 10% supply
■ Embedded erase and program algorithms
■ Hardware write protection
■ Page program operation and internal program control time.