Features
• 25MHz PFT clock delay management
• 85Ω Low-power push-pull HCSL outputs; eliminate 24
resistors, save 41mm2 of area
• Pin compatible to 9ZX21201 and 9ZXL1231; easy path to
power and area savings
• Space-saving 64-pin VFQFPN package
• Fixed feedback path for 0ps input-to-output delay
• 9 selectable SMBus addresses; multiple devices can share
the same SMBus segment
• 12 OE# pins; hardware control of each output
• PLL or bypass mode; supports common and separate clock
architectures
• Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLLs
• Spread spectrum compatible; tracks spreading input clock
for low EMI
• -40°C to +85°C device available; supports demanding
environmental applications