FEATURES:
• 2.3V to 2.7V Operation
• SSTL_2 Class I style data inputs/outputs
• Differential CLK input
• RESET control compatible with LVCMOS levels
• Flow-through architecture for optimum PCB design
• Drive up to equivalent of 14 SDRAM loads
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
• Available in TSSOP package
APPLICATIONS:
• Along with CSPT857C, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 DIMMs