1. General description
The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D),
clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the
D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will
be stored in the flip-flop and appear at the Q output.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures very low static and dynamic power consumption across the entire VCC range
from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
2. Features and benefits
• Wide supply voltage range from 0.8 V to 3.6 V
• CMOS low power dissipation
• High noise immunity
• Overvoltage tolerant inputs to 3.6 V
• Low static power consumption; ICC = 0.9 μA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Low noise overshoot and undershoot < 10 % of VCC
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.9 V to 1.65 V)
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F Class 3A exceeds 5 kV
• MM JESD22-A115-A exceeds 200 V
• CDM JESD22-C101E exceeds 1 kV
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C