Features
System Operation
 Dual Core Architecture (ARM9 + DSP) , including hardware accelerator
 Support system boot sequentially from ARM to DSP
 Support address remap function
 For two cores, all modules have unified address space
 Selectable JTAG debug method
 ARM9 debug only (default)
 DSP debug only
 ARM9+DSP dual core debug
 Selectable CPU booting method
 Boot from Nand Flash
 Boot from SPI nor flash
 Boot from UART device
 Boot from eMMc

Memory Organization
 Internal memory space for ARM processor
 Internal 16KB SRAM for ARM9 ICache
 Internal 16KB SRAM for ARM9 DCache
 Internal 2KB SRAM for ARM9 ITCM
 Internal memory space for DSP processor
 Internal 64KB SRAM for DSP Instruction L1 Memory
(Also config as 32KB Memory+32KB ICache by software)
 Internal 64KB SRAM for DSP Data L1 Memory
 Internal 40KB SRAM for DSP Instruction L2 Memory
 Internal 32KB SRAM for DSP Data L2 Memory
 Embedded 8KB ROM for CPU Boot
 Embedded 2KB SRAM for communication between two cores

 Processors
 ARM926EJC
 RISC architecture with 32bit ARM and 16bit Thumb instruction sets
 Include efficient execution of Java byte codes
 Built-in MMU to provide flexible memory management needed by many
mainstream OS
 Harvard cached architecture , separate ICache and DCache
 Separate instruction and data TCM interfaces
 Separate instruction and data AHB bus interface