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TDRV001-SW-72 Datasheet (PDF) - TEWS Technologies GmbH

TDRV001-SW-72 Datasheet PDF - TEWS Technologies GmbH
Part # TDRV001-SW-72
Download  TDRV001-SW-72 Download
File Size   76.32 Kbytes
Page   2 Pages
Manufacturer  TEWS [TEWS Technologies GmbH]
Direct Link  https://www.tews.com/
Logo TEWS - TEWS Technologies GmbH
Description 4 Channel High Speed Synch/Asynch Serial Interface

TDRV001-SW-72 Datasheet (PDF)

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TDRV001-SW-72 Datasheet PDF - TEWS Technologies GmbH

Part # TDRV001-SW-72
Download  TDRV001-SW-72 Click to download

File Size   76.32 Kbytes
Page   2 Pages
Manufacturer  TEWS [TEWS Technologies GmbH]
Direct Link  https://www.tews.com/
Logo TEWS - TEWS Technologies GmbH
Description 4 Channel High Speed Synch/Asynch Serial Interface

TDRV001-SW-72 Datasheet (HTML) - TEWS Technologies GmbH


TDRV001-SW-72 Product details

The TPMC862 is a standard single-width 32 bit PMC with four high speed serial data communication channels.
An Infineon PEF 20534 DMA Supported Serial Communication Controller (DSCC4) with integrated bus master PCI interface is used.
Several interrupt sources can generate interrupts on INTA for each channel. Interrupts can be enabled and disabled separately.
A 14.7456 MHz oscillator provides standard asynchronous baud rates. An additional 24 MHz oscillator is provided for other baud rates. A 10 MHz oscillator is used for the maximum synchronous baud rate of 10Mbit/s.
Each channel can support many serial communication protocols such as HDLC, SDLC, PPP, asynchronous, monosynchronous, bisynchronous.
Multiprotocol transceivers are used for the line interface. The physical interface can be selected by software individually for each channel as EIA-232, EIA-422, EIA-449, EIA-530, EIA-530A, V.35, V.36 or X.21.
The TPMC862 supports Receive Data (RxD +/-), Transmit Data (TxD +/-), Receive Clock (RxC +/-), Transmit Clock (TxC +/-), Ready-To-Send (RTS +/-), Clear-To-Send (CTS +/-), Carrier-Detect (CD +/-) and GND for each channel. Additionally serial channel three provides Data-Set-Ready (DSR3 +/-) and Data-Terminal-Ready (DTR3 +/-), both over front I/O only.
The DSCC4 contains a central receive and transmit FIFO of 128 long words (32 bit) each. Additionally each channel has a receive FIFO (17 long words deep) and a transmit FIFO (8 long words deep).
The TPMC862 provides front panel I/O via a HD68 SCSI-3 type connector and rear I/O via P14.
For First Time Users the Engineering Documentation TPMC862-ED is recommended. The Engineering Documentation includes TPMC862-DOC, schematics and data sheets.
Software Support (TDRV001-SW-xx) for different operating systems is available.




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