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SN74ALVCH162268DL Datasheet (PDF) - Texas Instruments

SN74ALVCH162268DL Datasheet PDF - Texas Instruments
Part # SN74ALVCH162268DL
Download  SN74ALVCH162268DL Download
File Size   584.09 Kbytes
Page   18 Pages
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments
Description 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

SN74ALVCH162268DL Datasheet (PDF)

Go To PDF Page Download Datasheet
SN74ALVCH162268DL Datasheet PDF - Texas Instruments

Part # SN74ALVCH162268DL
Download  SN74ALVCH162268DL Click to download

File Size   584.09 Kbytes
Page   18 Pages
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments
Description 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

SN74ALVCH162268DL Datasheet (HTML) - Texas Instruments


SN74ALVCH162268DL Product details

FEATURES
· Member of the Texas Instruments Widebus™
Family
· Operates From 1.65 V to 3.6 V
· Max tpd of 4.8 ns at 3.3 V
· ±24-mA Output Drive at 3.3 V
· B-Port Outputs Have Equivalent 26-W Series
Resistors, So No External Resistors Are
Required
· Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
· Latch-Up Performance Exceeds 250 mA Per
JESD 17
· ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH162268 is used for applications in
which data must be transferred from a narrow
high-speed bus to a wide, lower-frequency bus.
The device provides synchronous data exchange
between the two ports. Data is stored in the internal
registers on the low-to-high transition of the clock
(CLK) input when the appropriate clock-enable
(CLKEN) inputs are low. The select (SEL) line is
synchronous with CLK and selects 1B or 2B input
data for the A outputs.
For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single
storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be
presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot
and undershoot.




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