FEATURES
· Inputs Are TTL-Voltage Compatible
· 4.5-V to 5.5-V V CC Operation
· Max tpd of 7.6 ns at 5 V
· Typical V OLP (Output Ground Bounce)
<0.8 V at VCC = 5 V, TA = 25°C
· Typical V OHV (Output VOH Undershoot)
>2.3 V at VCC = 5 V, TA = 25°C
· Support Mixed-Mode Voltage Operation on All
Ports
· Ioff Supports Partial-Power Down Mode
Operation
· Latch-Up Performance Exceeds 250 mA Per
JESD 17
· ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION
The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding
or data-routing applications requiring very short propagation delay times. In high-performance memory systems,
this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories
utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less
than the typical access time of the memory. This means that the effective system delay introduced by the
decoder is negligible.