Minimum instruction execution time can be changed
from high speed (0.025 μs: @ 40 MHz operation with
high-speed on-chip oscillator clock or PLL clock) to ultra
low-speed (66.6 μs: @ 15 kHz operation with low-speed
on-chip oscillator clock)
General-purpose register: 8 bits × 32 registers (8 bits ×
8 registers × 4 banks)
ROM: 128 KB / 256 KB
RAM: 12 KB / 24 KB
Data flash memory: 8 KB / 16 KB
High-speed on-chip oscillator clock
Selectable from 40 MHz (Typ.), 32 MHz (Typ.), 20 MHz (Typ.),
16 MHz (Typ.), 8 MHz (Typ.), 4 MHz (Typ.), and 2 MHz (Typ.)
(Selectable from 80 MHz (Typ.) and 64 MHz (Typ.) when using
Timer RDe and RS-CANFD lite Note 1 )
Low-speed on-chip oscillator clock: 15 kHz × 2 ch (one
for WWDT and one for CPU and peripherals other than
WWDT)
On-chip PLL
On-chip single-power-supply flash memory
(with prohibition of block erase/writing function)
Self-programming
(with boot swap function/flash shield window function)
On-chip debug function
On-chip power-on-reset (POR) circuit and voltage
detector (LVD)
On-chip watchdog timer (operable with the dedicated
low-speed on-chip oscillator clock)
Multiply/divide/multiply & accumulate instructions are
supported
16 bits × 16 bits = 32 bits (Unsigned or signed)
32 bits ÷ 32 bits = 32 bits (Unsigned)
16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)