Ultra-Low Power Technology
 2.7 V to 5.5 V operation from a single supply
 Stop (RAM retained): 0.23 μA, (LVD enabled): 0.31 μA
 Halt (RTC + LVD): 0.60 μA
 Operating: 156.25 μA/MHz
16-bit RL78 CPU Core
 Delivers 41 DMIPS at maximum operating frequency of
32 MHz
 Instruction execution: 86% of instructions can be
executed in 1 to 2 clock cycles
 CISC architecture (Harvard) with 3-stage pipeline
 Multiply signed & unsigned: 16 x 16 to 32-bit result in 1
clock cycle
 MAC: 16 x 16 to 32-bit result in 2 clock cycles
 16-bit barrel shifter for shift & rotate in 1 clock cycle
 1-wire on-chip debug function
Main Flash Memory
 Density: 32 KB to 64 KB
 Block size: 1 KB
 On-chip single voltage flash memory with protection from
block erase/writing
 Self-programming with secure boot swap function and
flash shield window function
Data Flash Memory
 Data flash with background operation
 Data flash size: 4 KB
 Erase cycles: 1 million (typ.)
 Erase/programming voltage: 2.7 V to 5.5 V