Functional Description
The CY7C1613KV18, and CY7C1615KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR® II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common I/O devices.

Features
■ Separate independent read and write data ports
   ❐ Supports concurrent transactions
■ 333 MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
   ❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed systems
■ Single multiplexed address input bus latches address inputs for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ Quad data rate (QDR®) II operates with 1.5-cycle read latency when DOFF is asserted high
■ Operates similar to a QDR I device with one-cycle read latency when DOFF is asserted low
■ Available in × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
   ❐ Supports both 1.5 V and 1.8 V I/O supply
■ Available in 165-ball fine-pitch ball grid array (FBGA) package (15 × 17 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive high-speed transceiver logic (HSTL) output buffers
■ JTAG 1149.1 compatible test access port (TAP)
■ Phase Locked Loop (PLL) for accurate data placement