Description
The HD74CDCF2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The HD74CDCF2510B operates at 3.3 V VCC and is designed to drive up to five clock loads per output.

Features
• Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”
• Phase-lock loop clock distribution for synchronous DRAM applications
• External feedback (FBIN) pin is used to synchronize the outputs to the clock input
• No external RC network required
• Support spread spectrum clock (SSC) synthesizers
• Supports frequencies up to 140 MHz
• 0 to 85°C operating range