GENERAL DESCRIPTION
The MT28F322P3 is a high-performance, highdensity, nonvolatile memory solution that can significantly improve system performance. This new architecture features a two-memory-bank configuration that supports background operation with no latency.
A high-performance bus interface allows a fast page mode data transfer; a conventional asynchronous bus interface is provided as well.

FEATURES
• Flexible dual-bank architecture
    Support for true concurrent operation with zero latency
    Read bank a during program bank b and vice versa
    Read bank a during erase bank b and vice versa
• Basic configuration:
    Seventy-one erasable blocks
        Bank a (8Mb for data storage)
        Bank b (24Mb for program storage)
• VCC, VCCQ, VPP voltages
    2.7V (MIN), 3.3V (MAX) VCC
    2.2V (MIN), 3.3V (MAX) VCCQ
    3.0V (TYP) VPP (in-system PROGRAM/ERASE)
    12V ±5% (HV) VPP tolerant (factory programming compatibility)
• Random access time: 70ns @ 2.7V VCC
• Page Mode read access
    Eight-word page
    Interpage read access: 70ns @ 2.7V
    Intrapage read access: 30ns @ 2.7V
• Low power consumption (VCC = 3.3V)
    Asynchronous/interpage READ < 15mA
    Intrapage READ < 7mA
    WRITE < 20mA (MAX)
    ERASE < 25mA (MAX)
    Standby < 15µA (TYP), 50µA (MAX) @ 3.3V
    Automatic power save (APS) feature
• Enhanced write and erase suspend options
    ERASE-SUSPEND-to-READ within same bank
    PROGRAM-SUSPEND-to-READ within same bank
    ERASE-SUSPEND-to-PROGRAM within same bank
• Dual 64-bit chip protection registers for security purposes
• Cross-compatible command support
    Extended command set
    Common flash interface
• PROGRAM/ERASE cycle
    100,000 WRITE/ERASE cycles per block
• Fast programming algorithm VPP = 12V ±5%