6

8393CS-MCU Wireless-09/14

ATmega256/128/64RFR2

current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port

E

also

provides

functions

of

various

special

features

of

the

ATmega256/128/64RFR2.

3.2.10 Port F (PF7...PF0)

Port F is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port F output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port F pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port

F

also

provides

functions

of

various

special

features

of

the

ATmega256/128/64RFR2.

3.2.11 Port G (PG5…PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port G output buffers have symmetrical drive characteristics with both high

sink and source capability. However the driver strength of PG3 and PG4 is reduced

leakage current is smaller. As inputs, Port G pins that are externally pulled low will

source current if the pull-up resistors are activated. The Port G pins are tri-stated when

a reset condition becomes active, even if the clock is not running.

Port

G

also

provides

functions

of

various

special

features

of

the

ATmega256/128/64RFR2.

3.2.12 AVSS_RFP

AVSS_RFP is a dedicated ground pin for the bi-directional, differential RF I/O port.

3.2.13 AVSS_RFN

AVSS_RFN is a dedicated ground pin for the bi-directional, differential RF I/O port.

3.2.14 RFP

RFP is the positive terminal for the bi-directional, differential RF I/O port.

3.2.15 RFN

RFN is the negative terminal for the bi-directional, differential RF I/O port.

3.2.16 RSTN

Reset input. A low level on this pin for longer than the minimum pulse length will

generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to

generate a reset.

3.2.17 RSTON

Reset output. A low level on this pin indicates a reset initiated by the internal reset

sources or the pin RSTN.

3.2.18 XTAL1

Input to the inverting 16MHz crystal oscillator amplifier. In general a crystal between

XTAL1 and XTAL2 provides the 16MHz reference clock of the radio transceiver.

3.2.19 XTAL2

Output of the inverting 16MHz crystal oscillator amplifier.

3.2.20 AREF

Reference voltage output of the A/D Converter. In general this pin is left open.

3.2.21 TST

Programming and test mode enable pin. If pin TST is not used pull it to low.