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SLG46170 Datasheet(PDF) 69 Page - Dialog Semiconductor |
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SLG46170 Datasheet(HTML) 69 Page - Dialog Semiconductor |
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69 / 87 page  000-0046170-103 Page 68 of 86 SLG46170 17.0 Power On Reset (POR) 17.1 POR Overview The Power On Reset (POR) Macrocell will produce a high or “1” signal as an output when the device power supply (VDD) rises to approximately 1.4 V. The typical internal delay for POR to release POR_IO will be 1 ms + depending on the power slope, because there is adaptive power-up sequence. The next internal signal will be POR_CORE and then POR_IO_DLY, each of which is further delayed by approximately 1 µs. The rise of POR_IO_DLY will trigger the I/O pins to exit tri-state, and the device will become active. 17.2 POR Timing Diagram Figure 38. POR Timing Diagram VDD POR IO POR CORE POR_IO_DLY RST 1.4 V 1 ms + 1 s 1 s Output PAD Determined by function logic Tri-state Initial state determined by registers s[1:0] |
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